ASIC page

Many of the TTL parts were later replaced by the standard programmable devices, such as the popular PLA and PAL devices (what’s the difference?). The PAL22v10 was the most popular programmable device for many years. (Remember the reason for choosing this combination?) LSI Logic of Milpitas is the first ASIC vendor to offer customers the opportunity to make "customized" IC's according to their specification. The ASIC market has grown to a multi-billion dollar industry since then.

In the 80’s and early 90’s, the most commonly used ASIC’s were first channeled gate array and later on sea-of-gates. For this type of designs, all the transistors are prefabricated and the ASIC vendor just need to add the so-called personality layers (metals). Since all the transistors were pre-manufactured, even the ASIC cell libraries were designed by add only metal layers to create the most commonly used cells such as “and”, “or” and flip-flop cells.

The channeled gate array have routing channels between transistor rows and the sea-ofgate type of ASIC’s do not have dedicated routing channels. For this reason, channeled gate array can achieve utilization of up to 90% and sea-of-gate only up to 40%. In the late 90’s and today, the most commonly used ASIC’s is the so-called Customer owned tooling (COT) type of ASIC designs. The design is completely designed by the customer and the ASIC vendor is only responsible for manufacture the device. For the COT type of design, all layers must be manufactured. After a design is finished by a customer, the customer must order mask sets (like the negative for developing photographs). The mask cost runs around $250,000 for 0.18 um process, $500,000 for 0.13um process and close to a million dollars for the 90 nm process. Due to the high cost of masks, Silicon foundries have been running shared wafers to put multiple customers on the same wafer to reduce the cost for test chips. Some vendors call this cyber-shuttle. The cost for a 5mm x 5mm test chip on the cyber-shuttle costs about $50,000 for 0.18um process. Each customer will get around 40 parts back with the cybershuttle.

The industry has gone through 3 major phases in its short history until now and it is on the way to a so-called "platform" based phase.

During the first phase, the ASIC vendors not only supply silicon, but also design tools to their customers. These tools were mostly written on mainframe computers such as those offered by LSI logic, Fujitsu and Toshiba. Daisy and Valid were the early EDA tools vendors to provide technology independent design tools to logic designers. Fujitsu were the largest ASIC supplier during this period. The largest channeled gate array contained about 30000 gates.

During the second phase, customers adopted the approach of using third party design tools instead of using ASIC vendor design tools. ASIC vendors transitioned from channeled gate array to channel-less sea-of-gate approach. Synopsys played a major role in making HDL synthesis adopted by ASIC customers. ASIC vendors provide design kits to its customers. The largest channel-less gate array contained up to a few hundred thousand gates. The most successful company in this phase was LSI logic. They provided ASIC customers with the so-called "core-ware" to reduce time to market for large ASIC design projects.

During this third phase, customers were driven back to standard cell based design methodology. The major suppliers in this phase were TSMC, UMC and Charter Semiconductor. Both design tools and design kits were supplied by third party vendors such as Artisan Components, Avanti and Nurlogic. The ASIC vendors concentrated on process technology only. The size of a typical design can be a million to multi-million gates. Many independent semiconductor Intellectual Property (IP) companies came along to provide building blocks for the large system-on-a-chip designs. Some vendors specialized in standard cell designs, some focused on analog components and others focused on memory designs.